|Subject||OrangeLogic & Data-JCE|
□ Project Title : VDSL Chipset based on the FMT Line
□ Korean Company : Orange Logic Co.
Israeli Company : Data-JCE
□ Project Duration : March 1st 2003 ~ December 31st 2004 (22 months)
□ Objective of Project
The VERDI project was established for developing VDSL chip set based on FMT line code. The VERDI project comprises development of prototype of Digital Signal Processor chip, which realizes FMT algorithm and development of its interfacing with Analog Front End chip AD9876 of Analog Devices.
The Digital Signal Processor Chip includes Bit-Pump Module, which includes FMT transmitter and FMT receiver, and Frame Module, which includes Interleaver / Deinterleaver, FEC, Framer, Ethernet and UTOPIA interfaces.
□ Outcome of the Project
Bit Pump Design & Framer Design, Simulation, Bit Pump & Framer Implementation and testing, Framer and Bit Pump integration
For Testing or Debugging ASIC, Test/Debugging environment is very important because test point is very limited in ASIC. Emulation board can be used for design verification before fabrication and for debugging after fabrication. For the effective debugging, it is important that emulation environment should be very similar to ASIC and monitoring should be easy. Emulation board configuration and monitoring can be implemented via external UART. Hardware signal waveform can be captured in PC environment.
□ Cooperation & Benefits
Data-JCE and Orange-Logic are developing Bit pump and Framer at the same time. After finishing the separate design, two function blocks should be integrated and tested together.
Through this project, both companies gained the competitiveness in performance at the high band-width applications. Especially Orange-Logic raised revenue at the factory automation system.
□ Repayment of Grant
- Sales volume at the completion of project : US$ 209,028
- Completion of the royalty payment : US$ 5,226
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